/*
 * LAN8740A PHY Driver
 *
 * Copyright (c) 2016-2019 John Robertson
 *
 * This program is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 3 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#ifndef LAN_8740A_H
#define LAN_8740A_H

typedef enum {
    LAN8740_REG_EDPD_CROSSOVER_EEE = 16,
    LAN8740_REG_MODE_CONTROL_STATUS,
    LAN8740_REG_SPECIAL_MODES,
    LAN8740_REG_TDR_PATTERNS_DELAY_CONTROL = 24,
    LAN8740_REG_TDR_CONTROL_STATUS,
    LAN8740_REG_SYMBOL_ERROR_COUNTER,
    LAN8740_REG_SPECIAL_CONTROL_STATUS_INDICATIONS,
    LAN8740_REG_CABLE_LENGTH,
    LAN8740_REG_INTERRUPT_SOURCE_FLAG,
    LAN8740_REG_INTERRUPT_MASK,
    LAN8740_REG_PHY_SPECIAL_CONTROL_STATUS
} lan8740_register_t;

// LAN8740_TDR_CONTROL_STATUS
typedef enum {
    LAN8740_TCS_TDR_ENABLE = 1 << 15,
    LAN8740_TCS_TDR_A_TO_D_FILTER_ENABLE = 1 << 14,
    LAN8740_TCS_TDR_CHANNEL_CABLE_DEFAULT = 0x00 << 9,
    LAN8740_TCS_TDR_CHANNEL_CABLE_SHORTED = 0x01 << 9,
    LAN8740_TCS_TDR_CHANNEL_CABLE_OPEN = 0x02 << 9,
    LAN8740_TCS_TDR_CHANNEL_CABLE_MATCHED = 0x03 << 9,
    LAN8740_TCS_TDR_CHANNEL_CABLE_MASK = 0x03 << 9,
    LAN8740_TCS_TDR_OPERATION_COMPLETE = 1 << 8,
    LAN8740_TCS_TDR_CHANNEL_LENGTH_MASK = 0xFF
} lan8740_tdr_control_status_t;

// LAN8740_SPECIAL_CONTROL_STATUS_INDICATIONS
typedef enum {
    LAN8740_SCSI_DISABLE_AUTO_MDIX = 1 << 15,
    LAN8740_SCSI_MDIX = 1 << 13,
    LAN8740_SCSI_DISABLE_SQE = 1 << 11,
    LAN8740_SCSI_REVERSED_POLARITY = 1 << 4
} lan8740_special_control_status_indications_t;

// LAN8740_REG_CABLE_LENGTH
typedef enum {
    LAN8740_CL_LENGTH_MASK = 0xF000,
    LAN8740_CL_LENGTH_POSN = 12
} lan8740_cable_length_t;

// LAN8740_REG_INTERRUPT_SOURCE_FLAG
// LAN8740_REG_INTERRUPT_MASK
typedef enum {
    LAN8740_INT_WOL = 1 << 8,
    LAN8740_INT_ENERGYON = 1 << 7,
    LAN8740_INT_AUTO_NEG_COMPLETE = 1 << 6,
    LAN8740_INT_REMOTE_FAULT = 1 << 5,
    LAN8740_INT_LINK_DOWN = 1 << 4,
    LAN8740_INT_AUTO_NEG_LP_ACK = 1 << 3,
    LAN8740_INT_PARALLEL_DETECT_FAULT = 1 << 2,
    LAN8740_INT_AUTO_NEG_PAGE_RX = 1 << 1
} lan8740_interrupt_flag_t;

// LAN8740_REG_PHY_SPECIAL_CONTROL_STATUS
typedef enum {
    LAN8740_SCS_SPEED_10M = 1 << 2,
    LAN8740_SCS_SPEED_100M = 1 << 3,
    LAN8740_SCS_FULL_DUPLEX = 1 << 4,
    LAN8740_SCS_HCDSPEED_MASK = 0x07 << 2,
    LAN8740_SCS_ENABLE_4B5B_CODEC = 1 << 6,
    LAN8740_SCS_AUTO_NEG_DONE = 1 << 12
} lan8740_special_control_status_t;

// MDIO Manageable Device (MMD) Registers
typedef enum {
    LAN8740_MMD_DEVAD_PCS = 3,
    LAN8740_MMD_DEVAD_AUTO_NEG = 7,
    LAN8740_MMD_DEVAD_VENDOR = 30
} lan8740_mmd_devad_register_t;

// LAN8740_MMD_DEVAD_PCS
typedef enum {
    LAN8740_MMDINDX_PCS_CONTROL_1,
    LAN8740_MMDINDX_PCS_STATUS_1,
    LAN8740_MMDINDX_PCS_DEVICES_PRESENT_1 = 5,
    LAN8740_MMDINDX_PCS_DEVICES_PRESENT_2,
    LAN8740_MMDINDX_PCS_EEE_CAPABILITY = 20,
    LAN8740_MMDINDX_PCS_EEE_WAKE_ERROR = 22,
    LAN8740_MMDINDX_PCS_WAKEUP_CTRL_STATUS = 32784,
    LAN8740_MMDINDX_PCS_WAKEUP_FILTER_CFG_A,
    LAN8740_MMDINDX_PCS_WAKEUP_FILTER_CFG_B,
    LAN8740_MMDINDX_PCS_WAKEUP_FILTER_MASK_1 = 32801,
    LAN8740_MMDINDX_PCS_WAKEUP_FILTER_MASK_2,
    LAN8740_MMDINDX_PCS_WAKEUP_FILTER_MASK_3,
    LAN8740_MMDINDX_PCS_WAKEUP_FILTER_MASK_4,
    LAN8740_MMDINDX_PCS_WAKEUP_FILTER_MASK_5,
    LAN8740_MMDINDX_PCS_WAKEUP_FILTER_MASK_6,
    LAN8740_MMDINDX_PCS_WAKEUP_FILTER_MASK_7,
    LAN8740_MMDINDX_PCS_WAKEUP_FILTER_MASK_8,
    LAN8740_MMDINDX_PCS_MAC_RX_ADDR_A = 32865,
    LAN8740_MMDINDX_PCS_MAC_RX_ADDR_B,
    LAN8740_MMDINDX_PCS_MAC_RX_ADDR_C,
    LAN8740_MMDINDX_PCS_MISC_CONFIG,
} lan8740_mmd_indx_pcs_t;

// LAN8740_MMDINDX_PCS_WAKEUP_CTRL_STATUS
typedef enum {
    LAN8740_MMD_PCS_WUCSR_BROADCAST_EN = 1 << 0,
    LAN8740_MMD_PCS_WUCSR_MAGIC_PACKET_EN = 1 << 1,
    LAN8740_MMD_PCS_WUCSR_WAKEUP_FRAME_EN = 1 << 2,
    LAN8740_MMD_PCS_WUCSR_PERFECT_DA_EN = 1 << 3,
    LAN8740_MMD_PCS_WUCSR_BROADCAST_RXED = 1 << 4,
    LAN8740_MMD_PCS_WUCSR_MAGIC_PACKET_RXED = 1 << 5,
    LAN8740_MMD_PCS_WUCSR_WAKEUP_FRAME_RXED = 1 << 6,
    LAN8740_MMD_PCS_WUCSR_PERFECT_DA_RXED = 1 << 7,
    LAN8740_MMD_PCS_WUCSR_WOL_CONFIGURED = 1 << 8,
    LAN8740_MMD_PCS_WUCSR_PME_SELF_CLEAR = 1 << 9,
    LAN8740_MMD_PCS_WUCSR_RXD2_IS_PME = 1 << 10,
    LAN8740_MMD_PCS_WUCSR_LED2_LINK_SPEED = 0x00 << 11,
    LAN8740_MMD_PCS_WUCSR_LED2_nINT = 0x01 << 11,
    LAN8740_MMD_PCS_WUCSR_LED2_nPME = 0x02 << 11,
    LAN8740_MMD_PCS_WUCSR_LED2_LINK_ACT = 0x03 << 11,
    LAN8740_MMD_PCS_WUCSR_LED1_LINK_ACT = 0x00 << 13,
    LAN8740_MMD_PCS_WUCSR_LED1_nINT = 0x01 << 13,
    LAN8740_MMD_PCS_WUCSR_LED1_nPME = 0x02 << 13,
    LAN8740_MMD_PCS_WUCSR_LED1_LINK_SPEED = 0x03 << 13,
    LAN8740_MMD_PCS_WUCSR_DISABLE_INTERFACE = 1 << 15,
} lan8740_mmd_pcs_wakeup_ctrl_status_t;

// LAN8740_MMDINDX_PCS_WAKEUP_FILTER_CFG_A
typedef enum {
    LAN8740_MMD_PCS_WUF_CFGA_BROADCAST_EN = 1 << 8,
    LAN8740_MMD_PCS_WUF_CFGA_MULTICAST_EN = 1 << 9,
    LAN8740_MMD_PCS_WUF_CFGA_ADDR_MATCH_EN = 1 << 10,
    LAN8740_MMD_PCS_WUF_CFGA_TRIGGERED = 1 << 14,
    LAN8740_MMD_PCS_WUF_CFGA_ENABLED = 1 << 15
} lan8740_mmd_pcs_wakeup_filter_cfga_t;

// LAN8740_MMD_DEVAD_VENDOR
typedef enum {
    LAN8740_MMDINDX_VENDOR_DEVICE_ID_1 = 2,
    LAN8740_MMDINDX_VENDOR_DEVICE_ID_2,
    LAN8740_MMDINDX_VENDOR_DEVICES_PRESENT_1 = 5,
    LAN8740_MMDINDX_VENDOR_DEVICES_PRESENT_2,
    LAN8740_MMDINDX_VENDOR_STATUS = 8,
    LAN8740_MMDINDX_VENDOR_TDR_MATCH_THRESHOLD = 11,
    LAN8740_MMDINDX_VENDOR_TDR_SHORT_OPEN_THRESHOLD,
    LAN8740_MMDINDX_VENDOR_PACKAGE_ID_1 = 14,
    LAN8740_MMDINDX_VENDOR_PACKAGE_ID_2
} lan8740_mmd_indx_vendor_t;

#endif // LAN_8740A_H
